Technology & Engineering

VLSI Test Principles and Architectures

Design for Testability

Author: Laung-Terng Wang,Cheng-Wen Wu,Xiaoqing Wen

Publisher: Elsevier

ISBN: 9780080474793

Category: Technology & Engineering

Page: 808

View: 3970

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
Computers

System-on-chip Test Architectures

Nanometer Design for Testability

Author: Laung-Terng Wang,Charles E. Stroud,Nur A. Touba

Publisher: Morgan Kaufmann

ISBN: 012373973X

Category: Computers

Page: 856

View: 4194

Written by a stellar team of field experts, this title is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that allow VSLI designers, DFT practitioners, and students to master quickly System-on-Chip Test architectures, memory, and analog/mixed-signal designs.
Technology & Engineering

Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits

Author: M. Bushnell,Vishwani Agrawal

Publisher: Springer Science & Business Media

ISBN: 0306470403

Category: Technology & Engineering

Page: 690

View: 1507

The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.
Technology & Engineering

VLSI Test Principles and Architectures

Design for Testability

Author: Laung-Terng Wang,Cheng-Wen Wu,Xiaoqing Wen

Publisher: Elsevier

ISBN: 9780080474793

Category: Technology & Engineering

Page: 808

View: 4959

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
Computers

Skew-Tolerant Circuit Design

Author: David Harris

Publisher: Elsevier

ISBN: 0080541267

Category: Computers

Page: 300

View: 2054

As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial Provides incisive instruction and advice punctuated by humorous illustrations Includes exercises to test understanding of key concepts and solutions to selected exercises
Technology & Engineering

Trusted Digital Circuits

Hardware Trojan Vulnerabilities, Prevention and Detection

Author: Hassan Salmani

Publisher: Springer

ISBN: 3319790811

Category: Technology & Engineering

Page: 131

View: 6365

This book describes the integrated circuit supply chain flow and discusses security issues across the flow, which can undermine the trustworthiness of final design. The author discusses and analyzes the complexity of the flow, along with vulnerabilities of digital circuits to malicious modifications (i.e. hardware Trojans) at the register-transfer level, gate level and layout level. Various metrics are discussed to quantify circuit vulnerabilities to hardware Trojans at different levels. Readers are introduced to design techniques for preventing hardware Trojan insertion and to facilitate hardware Trojan detection. Trusted testing is also discussed, enabling design trustworthiness at different steps of the integrated circuit design flow. Coverage also includes hardware Trojans in mixed-signal circuits.
Technology & Engineering

Low Power Design Essentials

Author: Jan Rabaey

Publisher: Springer Science & Business Media

ISBN: 9780387717135

Category: Technology & Engineering

Page: 288

View: 8069

This book contains all the topics of importance to the low power designer. It first lays the foundation and then goes on to detail the design process. The book also discusses such special topics as power management and modal design, ultra low power, and low power design methodology and flows. In addition, coverage includes projections of the future and case studies.
Technology & Engineering

Digital Systems Testing and Testable Design

Author: Miron Abramovici,Melvin A. Breuer,Arthur D. Friedman

Publisher: Wiley-IEEE Press

ISBN: 9780780310629

Category: Technology & Engineering

Page: 672

View: 4238

This updated printing of the leading text and reference in digital systems testing and testable design provides comprehensive, state-of-the-art coverage of the field. Included are extensive discussions of test generation, fault modeling for classic and new technologies, simulation, fault simulation, design for testability, built-in self-test, and diagnosis. Complete with numerous problems, this book is a must-have for test engineers, ASIC and system designers, and CAD developers, and advanced engineering students will find this book an invaluable tool to keep current with recent changes in the field.
Technology & Engineering

ESL Design and Verification

A Prescription for Electronic System Level Methodology

Author: Grant Martin,Brian Bailey,Andrew Piziali

Publisher: Elsevier

ISBN: 9780080488837

Category: Technology & Engineering

Page: 488

View: 835

Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors! Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the world’s leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with ‘no links to implementation’, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption. ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today. Table of Contents CHAPTER 1: WHAT IS ESL? CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT CHAPTER 4: WHAT ARE THE ENABLERS OF ESL? CHAPTER 5: ESL FLOW CHAPTER 6: SPECIFICATIONS AND MODELING CHAPTER 7: PRE-PARTITIONING ANALYSIS CHAPTER 8: PARTITIONING CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG CHAPTER 10: POST-PARTITIONING VERIFICATION CHAPTER 11: HARDWARE IMPLEMENTATION CHAPTER 12: SOFTWARE IMPLEMENTATION CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS APPENDIX: LIST OF ACRONYMS * Provides broad, comprehensive coverage not available in any other such book * Massive global appeal with an internationally recognised author team * Crammed full of state of the art content from notable industry experts
Technology & Engineering

System Level Design with Rosetta

Author: Perry Alexander

Publisher: Elsevier

ISBN: 9780080498379

Category: Technology & Engineering

Page: 384

View: 2454

The steady and unabated increase in the capacity of silicon has brought the semiconductor industry to a watershed challenge. Now a single chip can integrate a radio transceiver, a network interface, multimedia functions, all the "glue" needed to hold it together as well as a design that allows the hardware and software to be reconfigured for future applications. Such complex heterogeneous systems demand a different design methodology. A consortium of industrial and government labs have created a new language and a new design methodology to support this effort. Rosetta permits designers to specify requirements and constraints independent of their low level implementation and to integrate the designs of domains as distinct as digital and analog electronics, and the mechanical, optical, fluidic and thermal subsystems with which they interact. In this book, Perry Alexander, one of the developers of Rosetta, provides a tutorial introduction to the language and the system-level design methodology it was designed to support. * The first commercially published book on this system-level design language * Teaches you all you need to know on how to specify, define, and generate models in Rosetta * A presentation of complete case studies analyzing design trade-offs for power consumption, security requirements in a networking environment, and constraints for hardware/software co-design
Technology & Engineering

Designing SOCs with Configured Cores

Unleashing the Tensilica Xtensa and Diamond Cores

Author: Steve Leibson

Publisher: Elsevier

ISBN: 9780080472454

Category: Technology & Engineering

Page: 344

View: 1945

Microprocessor cores used for SOC design are the direct descendents of Intel’s original 4004 microprocessor. Just as packaged microprocessor ICs vary widely in their attributes, so do microprocessors packaged as IP cores. However, SOC designers still compare and select processor cores the way they previously compared and selected packaged microprocessor ICs. The big problem with this selection method is that it assumes that the laws of the microprocessor universe have remained unchanged for decades. This assumption is no longer valid. Processor cores for SOC designs can be far more plastic than microprocessor ICs for board-level system designs. Shaping these cores for specific applications produces much better processor efficiency and much lower system clock rates. Together, Tensilica’s Xtensa and Diamond processor cores constitute a family of software-compatible microprocessors covering an extremely wide performance range from simple control processors, to DSPs, to 3-way superscalar processors. Yet all of these processors use the same software-development tools so that programmers familiar with one processor in the family can easily switch to another. This book emphasizes a processor-centric MPSOC (multiple-processor SOC) design style shaped by the realities of the 21st-century and nanometer silicon. It advocates the assignment of tasks to firmware-controlled processors whenever possible to maximize SOC flexibility, cut power dissipation, reduce the size and number of hand-built logic blocks, shrink the associated verification effort, and minimize the overall design risk. · An essential, no-nonsense guide to the design of 21st-century mega-gate SOCs using nanometer silicon. · Discusses today's key issues affecting SOC design, based on author's decades of personal experience in developing large digital systems as a design engineer while working at Hewlett-Packard's Desktop Computer Division and at EDA workstation pioneer Cadnetix, and covering such topics as an award-winning technology journalist and editor-in-chief for EDN magazine and the Microprocessor Report. · Explores conventionally accepted boundaries and perceived limits of processor-based system design and then explodes these artificial constraints through a fresh outlook on and discussion of the special abilities of processor cores designed specifically for SOC design. · Thorough exploration of the evolution of processors and processor cores used for ASIC and SOC design with a look at where the industry has come from, and where it's going. · Easy-to-understand explanations of the capabilities of configurable and extensible processor cores through a detailed examination of Tensilica's configurable, extensible Xtensa processor core and six pre-configured Diamond cores. · The most comprehensive assessment available of the practical aspects of configuring and using multiple processor cores to achieve very difficult and ambitious SOC price, performance, and power design goals.
Computers

Electronic Design Automation

Synthesis, Verification, and Test

Author: Laung-Terng Wang,Yao-Wen Chang,Kwang-Ting Cheng

Publisher: Morgan Kaufmann

ISBN: 9780123743640

Category: Computers

Page: 934

View: 4180

As semiconductor applications continue to advance and proliferate, the industry is increasingly dependent on design technologies for design closure and for meeting productivity goals. Electronic design automation (EDA), which has driven advances in design technologies for the past 30 years, will continue to play a critical role in the semiconductor food chain. This book brings together a set of core EDA topics which provides an essential, fundamental understanding of the EDA tasks and the design process. Collectively, these topics cover the core knowledge, software tools, algorithms, methodologies, and infrastructure required to optimize synthesis, verification, and manufacturing test of a functional and reliable integrated circuit.
Technology & Engineering

On-Chip Communication Architectures

System on Chip Interconnect

Author: Sudeep Pasricha,Nikil Dutt

Publisher: Morgan Kaufmann

ISBN: 9780080558288

Category: Technology & Engineering

Page: 544

View: 4180

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. On-Chip Communication Architecures is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends Detailed analysis of all popular standards for on-chip communication architectures Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts Future trends that with have a significant impact on research and design of communication architectures over the next several years
Technology & Engineering

Embedded DSP Processor Design

Application Specific Instruction Set Processors

Author: Dake Liu

Publisher: Morgan Kaufmann

ISBN: 0123741238

Category: Technology & Engineering

Page: 778

View: 857

This book provides design methods for Digital Signal Processors and Application Specific Instruction set Processors, based on the author's extensive, industrial design experience. Top-down and bottom-up design methodologies are presented, providing valuable guidance for both students and practicing design engineers. Coverage includes design of internal-external data types, application specific instruction sets, micro architectures, including designs for datapath and control path, as well as memory sub systems. Integration and verification of a DSP-ASIP processor are discussed and reinforced with extensive examples. FOR INSTRUCTORS: To obtain access to the solutions manual for this title simply register on our textbook website (textbooks.elsevier.com)and request access to the Computer Science or Electronics and Electrical Engineering subject area. Once approved (usually within one business day) you will be able to access all of the instructor-only materials through the ";Instructor Manual"; link on this book's full web page. * Instruction set design for application specific processors based on fast application profiling * Micro architecture design methodology * Micro architecture design details based on real examples * Extendable architecture design protocols * Design for efficient memory sub systems (minimizing on chip memory and cost) * Real example designs based on extensive, industrial experiences.
Computers

Embedded Computing

A VLIW Approach to Architecture, Compilers and Tools

Author: Joseph A. Fisher,Paolo Faraboschi,Clifford Young

Publisher: Elsevier

ISBN: 1558607668

Category: Computers

Page: 671

View: 8528

The fact that there are more embedded computers than general-purpose computers and that we are impacted by hundreds of them every day is no longer news. What is news is that their increasing performance requirements, complexity and capabilities demand a new approach to their design. Fisher, Faraboschi, and Young describe a new age of embedded computing design, in which the processor is central, making the approach radically distinct from contemporary practices of embedded systems design. They demonstrate why it is essential to take a computing-centric and system-design approach to the traditional elements of nonprogrammable components, peripherals, interconnects and buses. These elements must be unified in a system design with high-performance processor architectures, microarchitectures and compilers, and with the compilation tools, debuggers and simulators needed for application development. In this landmark text, the authors apply their expertise in highly interdisciplinary hardware/software development and VLIW processors to illustrate this change in embedded computing. VLIW architectures have long been a popular choice in embedded systems design, and while VLIW is a running theme throughout the book, embedded computing is the core topic. Embedded Computing examines both in a book filled with fact and opinion based on the authors many years of R&D experience. · Complemented by a unique, professional-quality embedded tool-chain on the authors' website, http://www.vliw.org/book · Combines technical depth with real-world experience · Comprehensively explains the differences between general purpose computing systems and embedded systems at the hardware, software, tools and operating system levels. · Uses concrete examples to explain and motivate the trade-offs.
Computers

Design-for-test for Digital IC's and Embedded Core Systems

Author: Alfred L. Crouch

Publisher: The Rosen Publishing Group

ISBN: 9780130848277

Category: Computers

Page: 349

View: 1663

"Design-for-Test for Digital IC's and Embedded Core Systems is filled with full-page graphics taken directly from the author's teaching materials. Every section is illustrated with flow-charts, engineering diagrams, and conceptual summaries to make learning and reference fast and easy. This book is a must for the engineers and managers involved in design and testing."--BOOK JACKET.
Computers

Logic Minimization Algorithms for VLSI Synthesis

Author: Robert K. Brayton,Gary D. Hachtel,C. McMullen,Alberto L. Sangiovanni-Vincentelli

Publisher: Springer Science & Business Media

ISBN: 1461328217

Category: Computers

Page: 194

View: 5351

The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen tation was created in the summer of 1982. The results of preliminary tests on a fairly large set of industrial examples were good enough to justify the publication of our algorithms. It is hoped that the strength and speed of our minimizer warrant its Italian name, which denotes both express delivery and a specially-brewed black coffee.
Technology & Engineering

Embedded System Design

Modeling, Synthesis and Verification

Author: Daniel D. Gajski,Samar Abdi,Andreas Gerstlauer,Gunar Schirner

Publisher: Springer Science & Business Media

ISBN: 1441905049

Category: Technology & Engineering

Page: 352

View: 3283

Embedded System Design: Modeling, Synthesis and Verification introduces a model-based approach to system level design. It presents modeling techniques for both computation and communication at different levels of abstraction, such as specification, transaction level and cycle-accurate level. It discusses synthesis methods for system level architectures, embedded software and hardware components. Using these methods, designers can develop applications with high level models, which are automatically translatable to low level implementations. This book, furthermore, describes simulation-based and formal verification methods that are essential for achieving design confidence. The book concludes with an overview of existing tools along with a design case study outlining the practice of embedded system design. Specifically, this book addresses the following topics in detail: . System modeling at different abstraction levels . Model-based system design . Hardware/Software codesign . Software and Hardware component synthesis . System verification This book is for groups within the embedded system community: students in courses on embedded systems, embedded application developers, system designers and managers, CAD tool developers, design automation, and system engineering.
Computers

Lean Architecture

for Agile Software Development

Author: James O. Coplien,Gertrud Bjørnvig

Publisher: John Wiley & Sons

ISBN: 0470970138

Category: Computers

Page: 376

View: 3612

More and more Agile projects are seeking architectural roots as they struggle with complexity and scale - and they're seeking lightweight ways to do it Still seeking? In this book the authors help you to find your own path Taking cues from Lean development, they can help steer your project toward practices with longstanding track records Up-front architecture? Sure. You can deliver an architecture as code that compiles and that concretely guides development without bogging it down in a mass of documents and guesses about the implementation Documentation? Even a whiteboard diagram, or a CRC card, is documentation: the goal isn't to avoid documentation, but to document just the right things in just the right amount Process? This all works within the frameworks of Scrum, XP, and other Agile approaches
Computers

Built-in test for VLSI

pseudorandom techniques

Author: Paul H. Bardell,William H. McAnney,Jacob Savir

Publisher: Wiley-Interscience

ISBN: 9780471624639

Category: Computers

Page: 354

View: 1801

This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing.